Semiconductor devices or “ICs” (integrated circuits) have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry,” has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than 50 nanometers across.
Today's CMOS technologies utilize silicide to reduce the resistivity of the active and poly-silicon gate regions and allow ohmic contact with the interconnect metal. This silicide is susceptible to migration causing shorts between the drain, body, source and gate which effectively kill the associated device. This defect mechanism, which may be referred to as silicide encroachment, is one of the top causes of yield loss affecting the CMOS technology. Because the process sequences for forming NFETs and PFETs differ, the mechanisms for the formation of encroachment defects on each are generally quite different. Therefore it is important to be able to monitor for encroachment defects on both transistor types. Furthermore, in order to eliminate these mechanisms as quickly as possible and to promptly react to excursions, it is desirable to be able to detect these encroachment defects as early as possible in the process sequence.
Test structures which may be tested in-line, as early as the first metal level, provide a way to detect encroachment defects. However, since leakages just one thousand times greater than the leakage of a good CMOS device may be sufficient to kill a device, only small numbers of devices may be tied together and tested simultaneously. The area required for probe pads consumes much more area than the CMOS structures themselves. Since failure rates measured in the parts per billion are desired, many of these test structures are necessary to effectively monitor for encroachment defects. A second disadvantage of using probe-able test structures is that time intensive failure analysis and scrapping of the entire wafer are required to isolate the actual encroachment defect. A third disadvantage is that the structures are only tested at metal 1 or later, which is long after the encroachment defects may have formed.
In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. VC inspection is the subject of U.S. Patent Application Publication number 20070222470 to Patterson et al., and U.S. Pat. No. 7,456,636 to Patterson et al., both of which are incorporated in their entireties herein by reference. In-line VC inspection includes scanning the wafer surface of a NFET device in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces charge on all electrically floating elements whereas any grounded elements remain at zero potential. This potential difference is visible to the SEM. However, detection of encroachment defects affecting PFET devices has proven to be more challenging, due to insufficient contrast when the VC inspection is applied. Therefore, what is needed is an improved structure for VC contrast detection of PFET silicide encroachment.